It is known that, during the design of a complex integrated circuit, it is often difficult to establish with certainty beforehand the most advantageous circuit configuration or the most suitable component to achieve a predetermined functional effect. For example, it may be difficult, if not impossible, to evaluate the best time constant for a certain function, or the most appropriate intervention threshold for a given circuit, or the ideal current which a current-generator should supply. Moreover, it may also be useful to test a section of the integrated circuit in several different operative conditions, for example, with and without a network for correcting a parameter, in order to evaluate the effect of the correction, as in the case of an "offset"-canceling circuit, the exclusion of which would allow the magnitude of the "offset" to be evaluated.
It is also known that, during the design of an integrated circuit, it may be convenient to leave the selection between several variants of the circuit configurations and/or parameters open, to permit the production of integrated circuits the general functional characteristics of which are substantially identical, but which satisfy slightly different applicational requirements.
Thus, to allow for the "design options" described above, it is often necessary, at the design stage, to provide for modifiable connections or for selectively addressable memory cells or registers which enable the inputs of associated circuit units to be modified so as to adopt different operative states in dependence on the states of the aforesaid modifiable connections or of the memory cells or registers.
The various options are then tested and, of these, the one which offers the functional characteristics closest to those desired is selected and the final topography of the integrated circuit to be put into production is consequently defined.
The known techniques for satisfying the design requirements described above provide for the use of terminals of the device by means of which connection may or may not be established, of fuses within the integrated circuit which can be broken by means of high currents applied between suitable terminals of the integrated circuit, of EPROM cells, of programmable register cells, or of different metallization masks for the various design options. All of these techniques, except for the last mentioned, take up quite large areas of the integrated circuit; in particular, the use of terminals of the device requires the formation of contact pads which, as is known, necessarily have large dimensions; fuses require wide metal connecting strips because of the high currents necessary to break them and are also unreliable; in addition to the space which they take up, EPROM cells also require a special manufacturing process. In any case, for all these techniques, it is necessary to provide piloting signals which, in order to control the integrated circuit, naturally have to be conducted to the corresponding points by means of suitable metal tracks which are also very bulky.
As is known to a designer of integrated circuits, after the most favorable design options have been defined, modification of the topography of the integrated circuit in order to recover the areas intended for the test components and/or connections often cannot be accomplished, and these areas are therefore inevitably lost, detracting from the compactness of the final integrated structure.
As regards the technique which provides for different metallization masks for the various options, that is, variations in the mask for the formation of the last layer of connections in the sequence of steps of the manufacturing process, the problem is not the area taken up since, in this case, additional components or connections are not necessary, but, rather, the cost and the time necessary to put it into practice. In fact, each variant to be tested corresponds to a different mask, which itself is quite expensive, and to the manufacture of a batch of test chips, which requires a very long waiting time to evaluate the test. This technique is therefore suitable only when the number of variants to be tested is very low.